The present invention is generally directed to data processors and, more specifically, to systems and methods for reducing power consumption in a data processor having a clustered architecture.
The demand for high performance computers requires that state-of-the-art microprocessors execute instructions in the minimum amount of time. A number of different approaches have been taken to decrease instruction execution time, thereby increasing processor throughput. One way to increase processor throughput is to use a pipeline architecture in which the processor is divided into separate processing stages that form the pipeline. Instructions are broken down into elemental steps that are executed in different stages in an assembly line fashion.
A pipelined processor is capable of executing several different machine instructions concurrently. This is accomplished by breaking down the processing steps for each instruction into several discrete processing phases, each of which is executed by a separate pipeline stage. Hence, each instruction must pass sequentially through each pipeline stage in order to complete its execution. In general, a given instruction is processed by only one pipeline stage at a time, with one clock cycle being required for each stage. Since instructions use the pipeline stages in the same order and typically only stay in each stage for a single clock cycle, an N stage pipeline is capable of simultaneously processing N instructions. When filled with instructions, a processor with N pipeline stages completes one instruction each clock cycle.
The execution rate of an N-stage pipeline processor is theoretically N times faster than an equivalent non-pipelined processor. A non-pipelined processor is a processor that completes execution of one instruction before proceeding to the next instruction. Typically, pipeline overheads and other factors decrease somewhat the execution advantage rate that a pipelined processor has over a non-pipelined processor.
An exemplary seven stage processor pipeline may consist of an address generation stage, an instruction fetch stage, a decode stage, a read stage, a pair of execution (E1 and E2) stages, and a write (or write-back) stage. In addition, the processor may have an instruction cache that stores program instructions for execution, a data cache that temporarily stores data operands that otherwise are stored in processor memory, and a register file that also temporarily stores data operands.
The address generation stage generates the address of the next instruction to be fetched from the instruction cache. The instruction fetch stage fetches an instruction for execution from the instruction cache and stores the fetched instruction in an instruction buffer. The decode stage takes the instruction from the instruction buffer and decodes the instruction into a set of signals that can be directly used for executing subsequent pipeline stages. The read stage fetches required operands from the data cache or registers in the register file. The E1 and E2 stages perform the actual program operation (e.g., add, multiply, divide, and the like) on the operands fetched by the read stage and generates the result. The write stage then writes the result generated by the E1 and E2 stages back into the data cache or the register file.
Assuming that each pipeline stage completes its operation in one clock cycle, the exemplary seven stage processor pipeline takes seven clock cycles to process one instruction. As previously described, once the pipeline is full, an instruction can theoretically be completed every clock cycle.
The throughput of a processor also is affected by the size of the instruction set executed by the processor and the resulting complexity of the instruction decoder. Large instruction sets require large, complex decoders in order to maintain a high processor throughput. However, large complex decoders tend to increase power dissipation, die size and the cost of the processor. The throughput of a processor also may be affected by other factors, such as exception handling, data and instruction cache sizes, multiple parallel instruction pipelines, and the like. All of these factors increase or at least maintain processor throughput by means of complex and/or redundant circuitry that simultaneously increases power dissipation, die size and cost.
In many processor applications, the increased cost, increased power dissipation, and increased die size are tolerable, such as in personal computers and network servers that use x86-based processors. These types of processors include, for example, Intel Pentium(trademark) processors and AMD Athlon(trademark) processors. However, in many applications it is essential to minimize the size, cost, and power requirements of a data processor. This has led to the development of processors that are optimized to meet particular size, cost and/or power limits. For example, the recently developed Transmeta Crusoe(trademark) processor reduces the amount of power consumed by the processor when executing most x86 based programs. This is particularly useful in laptop computer applications. Other types of data processors may be optimized for use in consumer appliances (e.g., televisions, video players, radios, digital music players, and the like) and office equipment (e.g., printers, copiers, fax machines, telephone systems, and other peripheral devices).
In general, an important design objective for data processors used in consumer appliances and office equipment is the minimization of cost and complexity of the data processor. One way to minimize cost and complexity is to exclude from the processor core functions that can be implemented with memory-mapped peripherals external to the core. For example, cache flushing may be performed using a small memory-mapped device controlled by a specialized software function. The cost and complexity of a data processor may also minimized by implementing extremely simple exception behavior in the processor core.
A wide-issue processor pipeline, in contrast, executes bundles of operations in multiple stages. In a wide-issue processor, multiple concurrent operations are bundled into a single instruction and are issued and executed as a unit. In a clustered architecture, the machine resources are divided into clusters where each cluster consists of one or more register files each of which is associated with a subset of the execution units of the data processor.
A problem exists in that, to process these bundled instructions, the wide-issue processor pipeline consumes a large amount of power. For instance, a wide-issue processor will commonly execute xe2x80x9cbundlesxe2x80x9d of operations in multiple stages, wherein each stage in the pipeline is as wide as the executed word. Because it is generally not possible to completely populate a wide instruction with useful work (i.e., instructions), it is necessary to insert xe2x80x9cdummyxe2x80x9d instructions (i.e., non-operations) to fill all available slots. The problem arises in that these inserted xe2x80x9cdummyxe2x80x9d instructions consume power at each stage. Additionally, in normal operation, wide-issue processors require insertion of explicit non-operations to schedule correctly program execution (i.e., a feature of wide-issue processors over traditional sequential processors), these non-operations also consume power at each execution stage. As another example, power consumption problems can occur when repeated processor execution of small code sequences occurs as tight loops while unnecessary time is spent and power is expended in the cache.
Many data processors are not designed with a low/no power consumption mode, let alone functional units of the same, and, therefore, power consumption cannot be sufficiently reduced. Excessive power consumption by wide-issue data processors remains a continuing problem.
Therefore, there is a need in the art for improved data processors in which the cost and complexity of the processor core is minimized while maintaining the processor throughput. In particular, there is a need for improved systems and methods for reducing power consumption in a wide-issue data processor. More particularly, there is a need for systems and methods capable of addressing wasted power and time associated with unnecessary cache accesses.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a data processor having a clustered architecture that comprises a plurality of clusters, an instruction cache and a power-down controller that operates to selectively reduce power consumption in the data processor. Primary objects of the principles hereof are to recognize power down conditions early in an instruction execution pipeline of a cluster, and, responsive thereto, to execute power reduction measures and, whenever possible, carry the same along within the pipeline. The principles hereof are well suited for implementation in data processors having multiple functional units that allow multiple operations to be explicitly executed in a single cyclexe2x80x94such processors are commonly referred to as wide-issue (or xe2x80x9cVLIWxe2x80x9d) processors.
According to one advantageous embodiment, each cluster comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The power-down controller monitors the instruction cache and each instruction execution pipeline to identify power-down conditions associated with the same and, in response to an identified power-down condition, at least one of: (i) bypasses performance of at least a portion of subsequent ones of the N processing stages associated with an executing instruction, (ii) powers down the instruction cache, and (iii) powers down the data processor.
An important aspect of the foregoing embodiment is that the principles of the present invention may suitably be focused upon the functionality of the instruction cache and each instruction execution pipeline. According to a related embodiment, three recognition techniques may be used while the power-down controller monitors the instruction cache and each instruction execution pipeline to reduce power consumption.
For instance, the data processor set forth above may further comprise an instruction fetch buffer, and an identified power-down condition may suitably indicate detection of at least one of (i) a non-operation in one of the clusters, (ii) a tight-loop condition in the instruction fetch buffer, or (iii) an idle-loop condition. By way of further example, the power-down controller, while performing its monitoring function, may operate to detect a non-operation associated with an instruction executing in an instruction execution pipeline of one of the clusters. The power-down controller, in response to detecting this non-operation, may bypasses performance of at least a portion of any subsequent processing stages, thereby reducing power consumption in the subsequent processing stages as the executing instruction passes through the instruction execution pipeline. Significant power reductions can be made in the execution of programs, whilst maintaining code compatibility.
According to another embodiment of the present invention, the data processor further comprising an instruction-fetch buffer. The power-down controller thereof operates to power down (i) the instruction cache in response to identifying a tight-loop condition in the instruction fetch buffer, or (ii) the data processor in response to identifying an idle-loop condition.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d and xe2x80x9ccircuitryxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device, system or part thereof may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller or circuitry may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.